IBM has built what it calls the world’s first 2-nanometer node chip.
As process nodes have shrunk into the single digits, the way companies quantify node measurements has splintered, with each company using a different metric that favours their approach.
The company said that it can fit 50 billion transistors onto a 150 square millimetre chip.
IBM claims that the 2nm chip could achieve 45 per cent higher performance, or 75 per cent lower energy use than ‘today’s most advanced 7nm node chips’.
This could allow for smartphones to last up to four days, the company said, or reduce the carbon footprint of data centres.
‘The IBM innovation reflected in this new 2nm chip is essential to the entire semiconductor and IT industry’, said Darío Gil, SVP and director of IBM Research.
‘It is the product of IBM’s approach of taking on hard tech challenges and a demonstration of how breakthroughs can result from sustained investments and a collaborative R&D ecosystem approach.’
It is not clear how long it will take for the technology to find its way into an actual product, with IBM releasing its first 7nm products later this year.
The company first hit the 5nm milestone for prototype chips some four years ago but has yet to develop its own hardware at that scale. Research partner Samsung entered volume production of 5nm in 2020.
IBM no longer has any chip factories, beyond small research production, after it paid GlobalFoundries to take its manufacturing business back in 2014.
At the time, the two companies signed a 10-year partnership, with GF serving as IBM’s primary chip manufacturer for its declining Power line.
This year, IBM said it would form a partnership with Intel to research next-generation logic and packaging technologies, following the launch of Intel’s own foundry business.
TSMC, the world’s largest contract chip manufacturer, expects to go into volume production of 4nm and 3nm next year and is working on 2nm technology.
But companies are beginning to hit some fundamental limitations with the laws of physics as they shrink transistors to try to keep compute densities rising.
A single human hair spans a whopping 50,000-75,000 nanometers. A human red blood cell is 6,000-8,000nm. Covid-19 is 50-140nm.
To build nodes 3nm and below requires extremely expensive and sensitive equipment, and a rethink on how nodes are laid out – hence the different metrics now used to measure smaller nodes.
Quantum effects also become more pronounced, leading some to question whether the cost and difficulty are worth it.
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But travel back less than a decade, and there are those that said 5nm would prove the fundamental limit of chip architectures.
More recent prognostication has put the limit at 3nm, something IBM has surpassed, depending on how you classify their metric – one in which details are currently quite limited.
Looking further, the Department of Energy’s Lawrence Berkeley National Laboratory was able to show that shrinking, even more, is at least theoretically possible.
In 2016, the research team created a transistor with a working 1nm gate, using carbon nanotubes and molybdenum disulfide. But they had yet to develop a viable method to mass-produce the transistor, or develop it on a chip.
